REV. A
ADM1027
39
OPERATING FROM 3.3 V STANDBY
The ADM1027 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor will be lowered in these states.
Note that since other voltages can drop or be turned off during
a low power state, these voltage channels will set status bits or
generate SMBALERTs. It is still necessary to mask out these
channels prior to entering a low power state by using the interrupt
mask registers. When exiting the low power state, the mask bits
can be cleared. This prevents the device from generating unwanted
SMBALERTs during the low power state.
XOR TREE TEST MODE
The ADM1027 includes an XOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XOR tree, it is
possible to detect opens or shorts on the system board. Figure 43
shows the signals that are exercised in the XOR tree test mode.
The XOR tree test is invoked by setting Bit 0 (XEN) of the
XOR tree test enable register (Reg. 0x6F).
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
VID4
VID3
VID2
VID1
VID0
Figure 43. XOR Tree Test
Rev. 3 | Page 39 of 56 | www.onsemi.com
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